The present invention relates to electronic circuits, and more particularly, to input/output interface circuits for periodic signals.
FIG. 1 illustrates an example of a prior art interface circuit 100 on an integrated circuit. Interface circuit 100 includes buffer circuit 102, phase-locked loop 103, a circuit 106 that contains 7 counter circuits, multiplexer circuits 111-116, single-ended buffer circuits 121-127, differential buffer circuits 131-132, and external pins 101 and 141-146.
Buffer circuit 102 buffers an input clock signal CLKIN received from pin 101 to generate a reference clock signal CLKREF at an input of phase-locked loop (PLL) circuit 103. PLL 103 generates output clock signals CLKOUT using voltage-controlled oscillator (VCO) 104 in response to reference clock signal CLKREF. The counter circuits in circuit 106 divide the frequencies of output clock signals CLKOUT to generate 6 frequency divided clock signals CLK0-CLK5. Multiplexer circuits 111-116 are configured to provide clock signals CLK0-CLK5 to inputs of buffer circuits 121-126, respectively. In a feedback mode, one of the 6 frequency divided clock signals CLK0-CLK5 is the source of clock signal CLKX. CLKX is transmitted to a counter circuit in circuit 106 that multiplies the frequency of clock signal CLKX to generate the feedback clock signal CLKFB for PLL circuit 103. The frequency of CLKFB is the same as the frequency of clock signal CLKIN and signal clock signal CLKREF.
When buffer circuits 123 and 127 are enabled in a mode of operation referred to as zero delay buffer mode, buffer circuit 127 buffers the output clock signal of buffer circuit 123 to generate a buffered clock signal CLKX that is provided to one of the counter circuits in circuit 106. The counter circuit multiplies the frequency of clock signal CLKX to generate a frequency multiplied feedback clock signal CLKFB that is provided to an input of PLL 103. PLL 103 compares the phases and frequencies of CLKREF and CLKFB to generate clock signals CLKOUT.
When buffer circuits 121-122 and 127 are enabled and buffer circuit 123 is disabled in a mode of operation referred to as single-ended external feedback mode, buffer circuits 121-122 buffer the output clock signals of multiplexers 111-112 to generate single-ended clock signals at pins 141-142, respectively. One of these single-ended clock signals is transmitted through external conductors (not shown) to pin 143. Buffer circuit 127 buffers the clock signal received at pin 143 to generate a buffered clock signal CLKX that is provided to the counter circuit in circuit 106 generating feedback clock signal CLKFB.
When differential buffer circuits 131-132 are enabled and buffer circuits 121-124 and 127 are disabled in a mode of operation referred to as differential external feedback mode, differential buffer circuit 131 buffers the output clock signal of multiplexer 111 to generate a differential clock signal at pins 141-142. The differential clock signal is transmitted through external conductors (not shown) to pins 143-144. Differential buffer circuit 132 buffers the differential clock signal received at pins 143-144 to generate a buffered single-ended clock signal CLKX. CLKX is provided to the counter circuit in circuit 106 that generates feedback clock signal CLKFB.